1. Field of the Invention
The present invention relates to a multi cap layer and manufacturing method thereof, and more particularly, to a multi cap layer used in damascene interconnect processes.
2. Description of the Prior Art
Damascene interconnect processes incorporated with copper are known in the art, which are also referred to as “copper damascene processes” in the semiconductor industry. Generally, the copper damascene processes are categorized into single damascene process and dual damascene process. Because the dual damascene has advantages of simplified processes, lower contact resistance between wires and plugs, and improved reliance, it is widely applied in damascene interconnect technique. In addition, to reducing resistance and parasitic capacitance of the multi-level interconnect and improving speed of signal transmission, the dual damascene interconnect in state-of-the-art is fabricated by filling trench or via patterns located in dielectric layer which comprise low-K material with copper and performing a planarization process to obtain a metal interconnect. According to the patterns located in the dielectric layer, the dual damascene process is categorized into trench-first process, via-first process, partial-via-first process, and self-aligned process.
Please refer to FIGS. 1-5, which are schematic drawings of a conventional trench-first dual damascene process. As shown in FIG. 1, a substrate 10 having a conductive layer 12 and a base layer 14 comprising silicon nitride sequentially formed thereon is provided. And an ultra low-k (ULK) dielectric layer 16, a cap layer 18, a metal hard mask layer 20, and a bottom anti-reflective coating (BARC) layer 22 are sequentially formed on the base layer 14. Then, a photoresist layer 30 is formed and patterned to form an opening 32 by a well-known photolithography method. The opening 32 is used to define a trench pattern of a damascene structure.
Subsequently, as shown in FIG. 2, an etching process is performed. A trench recess 34 is etched into the metal hard mask layer 20 and the cap layer 18 through the opening 32. The etching is stopped on the cap layer 18. The remaining photoresist layer 30 and the BARC layer 22 are then stripped off.
As shown in FIG. 3, another BARC layer 36 is coated over the substrate 10 and fills the trench recess 34. And another photoresist layer 40 is formed on the BARC layer 36. The photoresist layer 40 has an opening 42 patterned by a conventional photolithography method. The opening 42 is situated directly above the trench recess 34 and is used to define a via pattern of a damascene structure. As shown in FIG. 4, the BARC layer 36, the cap layer 18, and the ULK layer 16 are etched through the opening 42 with the photoresist layer 40 being an etching mask. Thus, a partial via feature 44 is formed in an upper portion of the ULK layer 16. Then the remaining photoresist layer 40 and the BARC layer 36 are stripped off by using oxygen plasma.
Please refer to FIG. 5. Next, the metal hard mask layer 20 is used as an etching hard mask in an etching process, which is performed to etch away the cap layer 18 and the ULK layer 16 through the trench recess 34 and the partial via 44, thereby a dual damascene pattern comprising a trench opening 52 and a via opening 54 is obtained.
Generally, the cap layer 18 is a silicon oxide layer such as a tetra-ethyl-ortho-silicate (TEOS) based silicon oxide layer with TEOS used as a precursor. The TEOS layer comprises a compressive stress. When the TEOS layer contacts the ULK layer 16 directly, the compressive stress of the TEOS layer causes line distortion in the ULK layer 16. Moreover, since the TEOS layer is apt to absorb water, the absorbed water is then desorpted in following process and gets into the ULK layer 16, thus Kelvin via open are formed, which will reduce reliability of the process and influence electrical performance of the damascene interconnects formed followed.